Veeco's solutions provide the high performance and low cost of ownership required to support advanced packaging needs.
As the world around us becomes increasingly mobile and interconnected, consumers need solutions that enable them to access growing amounts of data at higher speeds, with lower power consumption, better performance and increased bandwidth.
The traditional approach to improve electronic device performance by scaling integrated circuit features to smaller and smaller dimensions has become increasingly costly and complex. As a result, semiconductor manufacturers are turning to new innovative packaging techniques, such as Fan-Out Wafer-level Packages (FOWLPs), which enable higher input/output (I/O) counts, and 3D packages, which vertically stack different types of semiconductor chips that are electrically connected using through silicon vias (TSVs).
The introduction of 3D packages in high-volume production has been hindered by the need to further reduce production costs and improve process control. For example, the silicon device wafer needs to be thinned to reveal the copper TSVs so the 3D connections can be made. However, accomplishing this has traditionally required four separate steps (grinding, polishing, cleaning and plasma etch), which are needed to remove the excess silicon and eliminate residual defects that can cause stress in the thinned wafer and lead to additional bowing and wafer breakage.
Veeco’s Precision Surface Processing solutions provide the high performance and low cost of ownership required to support the advanced packaging needs of outsourced semiconductor assembly and test (OSAT) providers and foundries.
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