Veeco PSP White Paper: Wet Etch TSV Reveal Process More Cost Effective Than Dry Etch

Veeco PSP White Paper: Wet Etch TSV Reveal Process More Cost Effective Than Dry Etch

Product News | Mar 29, 2016

A Smarter, Cleaner Way to Prep TSVs

As chips get smaller and more advanced, Through Silicon Vias (TSVs) have become a go-to solution for connecting layers of silicon vertically. But creating those vertical pathways isn’t clean work—Deep Reactive Ion Etching (DRIE) leaves behind stubborn polymers and photoresist residues that have to be removed before you can move on. Traditionally,
that has meant a combo of dry plasma “ash” and wet chemical cleans.

Veeco’s new study shows there’s a simpler, more efficient way to get the job done.

The Twist: All-Wet Cleaning That Delivers

Teaming up with Dynaloy and SUNY Polytechnic Institute, Veeco developed a wet-only clean process that skips the ash step entirely. The method uses Dynastrip™ DL9150, a safer, TMAH-free chemistry, along with Veeco’s WaferStorm® system to combine a heated solvent soak with a high-pressure spray. It’s easier on the environment, gentler on the wafers—and it cuts out unnecessary steps.

Does It Work? Yep—And Here’s the Proof

The process was tested on TSVs of different sizes using SUNY Poly’s standard flow. Researchers evaluated everything from leakage current and dielectric breakdown voltage to surface cleanliness using SEM and Auger spectroscopy.

What They Found:

• The wet-only clean removed residues as well or better than traditional methods.
• Electrical performance held strong, with leakage & breakdown data matching standard benchmarks.
• Skipping the ash step shaved 33% off RIE time—a big win for cost and throughput.
• The chemistry is safer and still plays nice with sensitive materials.

The Takeaway

Veeco’s wet-only TSV clean checks all the right boxes: simpler, safer, and just as effective. For manufacturers aiming to streamline their 3D chip workflows, it’s a smart step forward—no ash required.

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