Blogs | Jan 26, 2021
By John Taddei, Director, Process Development Engineering
Semiconductor design has always been driven by the need to increase computational output per unit space while reducing power required to complete the task. The rate of this improvement has been characterized by Moore’s Law. Historically this has mainly been an endeavor of simply decreasing geometries. While shrinking geometries continues, in more recent years the search for performance has evolved into more complex series of paths, depending on the application. These paths include: alternate substrates (SiC, InP, InSb), new uses materials (Ru, Co, SiGe, GaN, WS, MoS) and the implementation of advanced packaging. Advanced Packaging has had an evolution of its own with variations at every level: 2.5D (interposer), 3D (die stacking), Wafer to Wafer bonding and heterogeneous integration (Chiplets and Die lets) to mention a few. Current drivers for the increased performance include: artificial intelligence (AI), data center demand, 5G\6G communications, Internet of things (IoT) and autonomous driving.
Specifying the correct etch tool is an application specific process. Automated wet etch originated in bench systems. While inexpensive and
offering high throughput, these systems suffered from poor process control within wafer, wafer to wafer and lot to lot. There were signatures from the etch process based on position in the cassette and wafer orientation. Open bath systems were high in defectivity, chemical usage, waste creation and open baths were a safety hazard. Batch spray systems maintained high throughput and offered better process control compared to a wet bench but still suffered from non-optimal performance. Single wafer emerged as the technology to permit each wafer to see the same process and obtain identical results. The advantages of single wafer were clear: best uniformity, highest repeatability, lowest defectivity processes. These results were obtained within a safe toolset that offered low chemical usage and minimal waste creation.
Single wafer wet etch was adopted in mainstream semiconductor manufacturing to provide consistent process in high volume manufacturing applications while delivering the lowest COO. Tight concentration, temperature and flow control was sufficient to drive a high quality, high repeatability process. End point detection was introduced to minimize undercut, uniformity variation, chemical usage and waste, while boosting throughput and lowering COO. Single wafer is the ideal platform as the end point can be called for each wafer, whereas batch spray or wet bench systems cannot adjust the process for each wafer. The mindset was that the best etch tool would accomplish its process and not induce variation in the product it produced. The continuous drive for enhanced performance now dictates that this net zero performance is insufficient. The process flow demands that the etch process now needs to correct for upstream variations in the manufacturing loop in order to deliver higher yielding product. The single wafer platform is now evolving and using its attributes once dedicated to deliver unsurpassed repeatability to deliver ultimate flexibility- a unique process to each wafer.
Wafer thinning has been employed to alter surface roughness and remove stress from grind. Incoming wafers to the etch process were of varying thickness with large TTV. A repeatable etch process would make the surface rougher or smoother as desired but thickness variation and TTV would remain unchanged. Newer applications demand value added etching where the radial TTV is improved and variations in grind thickness are addressed. Wafer thickness measurement (or the ability to accept external measurements) must be built into the tool and the software must be capable of changing etch profiles and etch time wafer to wafer to deliver a consistent end product from inconsistent incoming wafers. TSV reveal and via-less reveal processes are becoming more widely used, each with its own subtle variations. In addition to profile correction and etch depth control these applications require secondary, selective etching. Wafer thinning chemistries that offer an isotropic, high etch rate process are ideal for sculpting, surface texture control and correcting profiles in a timely manner. These chemistries are not compatible with via materials and materials such as bond pads that are exposed in reveal processes. Accordingly, a second etchant is used that is selective to the exposed materials. Additional challenges arrived in the form of alternate substrate composition or film material. This requires use of alternate chemistries that are capable of yielding results with the process window. As a result, higher end HVM etch tools incorporate provisions to have multiple active chemistries always available. Higher end R&D tools require the ability to change chemistries in a timely manner.
Manufacturing historically was widely done on full thickness, SEMI standard wafers. New process flows demand automated tools be capable of handling and processing multiple wafer diameters on the platform. The thickness and wafer composition will vary along with the diameter. Thin wafers, standard wafers, carrier wafers, reconstituted wafers, bonded wafers and even wafers on tape frame may be required to be processed on the same tool. An additional issue may arise on exclusion zones for each substrate type on where tooling can contact during the handling and process cycles. As the demands on manufacturing increase, so do the demands on tool suppliers. Tools are required to deliver higher throughputs at lower COO.
TSV Reveal- PMT ensures uniform reveal height UBM Etch- EPD undercut = film depth
EPD single point
The challenges in etch tool specification are increasing. This is driven by the need for increasing device performance to meet the demands of artificial intelligence, data centers demand, 5G\6G communications, Internet of things and autonomous driving. At a minimum tighter concentration, temperature, flow, smart chemical management and monitoring are required to deliver a capable toolset with low COO. Advanced packing is supplementing geometry reduction for boosting performance. More demanding applications require the etch tool to correct for upstream process steps. On board metrology, adaptive process recipe creation and choice of selective chemistry are requirements on these demanding applications. Process flows with wafers on frame, temporary bonding and thin wafers drive the need for flexible handling and processing capability. The need to specify and design an application specific etch tool is increasing. Platforms that are flexible and adaptable are the ones capable of incorporating application specific technology to provide today’s solutions.