Chip Scale Review - Photoresist Strip Using Advanced Single-Wafer Process Technology

Chip Scale Review – Photoresist Strip Using Advanced Single-Wafer Process Technology

Product News | Dec 01, 2016

Why Wet Etch Wins in 3D-IC Manufacturing for TSV Reveal

As 3D integrated circuits (3D-ICs) become more common, manufacturers are looking for smarter ways to boost performance, cut costs, and free up valuable factory space. A study commissioned by Veeco shows how wet etching checks all those boxes—outperforming traditional dry etch methods in key steps like backside wafer thinning and via-revealing.

Tackling TSV Challenges

3D-ICs use through-silicon vias (TSVs) to connect different layers of a chip. That makes backside processing a critical part of the equation. After grinding the wafer, manufacturers rely on dry etching, and CMP to perform the TSV reveal. This combines plasma etching, CMP, and multiple cleaning steps. It’s a complicated, expensive process that requires several tools and raises the risk of wafer defects.

A Simpler, Smarter Wet Etch Approach

Veeco takes a different path. Our wet etch process uses a single WaferEtch® tool to do the work of four separate machines: CMP, plasma etch, cleaning, and metrology. This two-step, liquid-based etch thins silicon fast, efficiently, and safely, revealing the TSV—and it delivers a cleaner, higher-quality wafer.

Key Benefits

1. Lower Costs – Cuts TSV reveal processing expenses by more than 50%
2. Smaller Factory Footprint – Replaces multiple tools with one compact system
3. Better Wafer Quality – Produces smoother, more uniform surfaces with fewer defects
4. Safer Chemistry – Eliminates toxic etchants like TMAH

The Bottom Line

Wet etch isn’t just a viable alternative—it’s a smarter solution. With better cost efficiency, scalability, and yield, Veeco’s wet etch approach is ready to meet the demands of next-generation semiconductor packaging.

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